| 摘要 |
PCT No. PCT/JP97/00336 Sec. 371 Date Oct. 3, 1997 Sec. 102(e) Date Oct. 3, 1997 PCT Filed Feb. 7, 1997 PCT Pub. No. WO97/29485 PCT Pub. Date Aug. 14, 1997In a data decoding apparatus of this invention, level of a reproduction RF signal 7a at the time of the binary level judgment of channel bit is temporarily stored into a RF signal level memory section 20. The portions which do not satisfy the conditions of the minimum run length and the maximum run length of the same symbols within the channel bit data train are respectively detected by a (d'-1) detecting section 16 and a (k'+1) detecting section 17. This data decoding apparatus comprises correction bit position detecting sections 18, 19 for outputting correction bit position designation signals on the basis of level of the RF signal at the time of the binary level judgment stored in the RF signal level memory section 20, and a bit data inversion correcting section 15 for inverting logic level of data at bit position designated on the basis of the correction bit position designation signals 18a, 18b, 19a, 19b. In the case where there exists any portion which does not satisfy the conditions of the minimum run length and/or the maximum run length of the same symbols within channel bit data obtained by binarizing a signal which has been read out from the recording medium, correction is implemented to the channel bit data, thereby making it possible to improve the bit error rate, and to ensure skew margin.
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