| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an image processor small in circuit scale and little in power consumption. SOLUTION: Digital image processing in an effective pixel period is performed while 1st internal logic description is written in a field programmable gate array 106. Next, digital control processing is performed while the 1st internal logic description in the array 106 is rewritten into 2nd internal logic description in an ineffective pixel period other than the effective pixel period and subsequently, digital image processing is performed while the 2nd internal logic description in the array 106 is rewritten into the 1st internal logic description again.</p> |
