Multi-cycle I/O ASIC communication system having an arbiter circuit capable of updating address table associated with each I/O ASIC on bus

摘要

An arbiter circuit is employed to isolate a processor from a plurality of Input/Output Application Specific Integrated Circuits ("I/O ASICs"). The processor is coupled to the arbiter through a control bus, an address bus and a data bus. The arbiter is coupled to the I/O ASICs through an extension of the control bus and a combined address/data bus. The arbiter manages control of the control bus extension and address/data bus to enable contemporaneous transmission ("broadcast") of messages to the I/O ASICs, and enable the processor to access the I/O ASICs. Only one of the I/O ASICs is granted control of the control bus extension and address/data bus at any point in time. The processor may also be granted sole control of the control bus extension and address/data bus.