High-voltage transistor with multi-layer conduction region

摘要

A high voltage insulated gate-effect transistor includes an insulated gate field-effect device structure having a source (14) and a drain (19), the drain (19) being formed with an extended well region (17) having one or more buried layers (18) of opposite conduction type sandwiched therein. The one or more buried layers (18) create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.