| 摘要 |
PROBLEM TO BE SOLVED: To reduce the memory capacity of FIFO(first-in first-out) in order to obtain a prescribed delay time. SOLUTION: An input side logical part 13a executes initialization at the input side of the FIFO circuits 11(11a-11n) by an indication from a delay setting control part 2. A frame pulse signal 103 and an elementary stream(ES) data effective signal 102 are inputted and an input permitting signal 111a is outputted, and then ES data 101 are stored in the each FIFO circuit 11 at every packet. After the prescribed delay time elapses, initialization is executed at the output side of the FIFO circuits 11 by an output side logical part 13b by the indication from the control part 2 and stored ES data 101 is read by an output rate pulse signal 106. A selecting part 14 selects the outputs of the FIFO circuit 11 and outputs them as raster stream data 104.
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