发明名称 TEST DEVICE AND TEST METHOD
摘要 PROBLEM TO BE SOLVED: To detect the error of a reception packet without the need of an expensive externally mounted circuit which is used for CRC(cyclic redundancy checksum) calculation, for example. SOLUTION: A serial/parallel(S/P) conversion circuit 110 converts inputted reception data into parallel data in accordance with a timing signal which a timing generation circuit 120 generates and outputs it to a CPU 130. The CPU 130 refers to data inputted from the S/P conversion circuit 110, retrieves prescribed diagnosis information stored in a memory 140 such as CRC and PN(pseudo random number) codes. An error detection means compares prescribed diagnosis information such as the CRC and PN codes with CRC and PN codes in reception data and executes the error detection processing of the reception packet.
申请公布号 JP2000232448(A) 申请公布日期 2000.08.22
申请号 JP19990033168 申请日期 1999.02.10
申请人 NEC CORP 发明人 KACHI YASUSHI
分类号 G01R31/00;H04B17/00;H04L12/26;H04L12/70 主分类号 G01R31/00
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