| 摘要 |
To form a shallow well MOSFET, an epitaxial layer is subjected to a blanket implant of impurities, so as to form a very shallow well region that defines a PN junction with the epitaxial layer. A field oxide layer is selectively formed on a portion of the shallow well region, and a gate insulator layer is formed on the exposed portion of the shallow well region contiguous with the field insulator layer. A polycrystalline silicon spacer-gate layer is non-selectively deposited on the field insulator layer and the gate insulator layer, forming a multiple thickness implant mask. The resulting structure is subjected to one or more high energy impurity implants, to overdose and thereby convert a portion of the shallow well region to the conductivity of the epitaxial layer. This extends the PN junction up to the surface of the well region beneath the gate insulator layer, thereby defining the length of the channel between the side edge of the field oxide layer and the extended PN junction. A polysilicon planarization layer is then non-selectively formed on the spacer layer, followed by a planarization etch, to define the thickness of the gate layer. The field insulator layer is then stripped, and source and drain regions are formed. What results is a shallow well insulated gate field effect semiconductor device having decreased resistance and current pinching in the channel neck region, relative to that of a conventional process, thereby providing increased power handling capability and efficiency.
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