FLIP-FLOP CIRCUIT WITH CLOCK SIGNAL CONTROLLING FUNCTION AND CLOCK CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To suppress the power consumption of a flip-flop circuit. SOLUTION: The flip-flop circuit 10 is provided with a mismatch detecting circuit DDC and a clock controlling circuit CCC. The circuit DDC detects mismatch between a data input signal DIS and a data output signal DOS of the circuit 10. When the signal DIS and the signal DOS are mismatched, the circuit CCC supplies a short pulse for the circuit 10 as an internal clock signal ICLK by synchronizing with the rising of an external clock signal ECLK. Whereas, when the signal DIS and the signal DOS match with each other, the circuit CCC supplies a low-level signal for the circuit 10 as the signal ICLK. Thus, it is possible to avoid generating of an error in flip-flop operation while suppressing power consumption required for supplying a clock signal.