发明名称 MULTI-CHIP/CHIP SCALE INTEGRATED CIRCUIT PACKAGE
摘要 <p>PURPOSE: A package is provided to improve a chip operation and heat dissipation. It also performs a test process of chip package without using good known die(KGD) technology during a packing process. CONSTITUTION: A film carrier(58) including an insulation film(54) and many conductive wires(56) loads two chips(50,52). Surfaces(60,62) of two chips are placed face to face. Many conductive bumps(64) are formed on a face(60) of a first chip(50). Each bump and surface is connected electrically to one out of many bonding pads. Many second bumps(66) are formed on a face(62) of a second chip(52). In a case, each bump and surface is also connected electrically to one out of many bonding pads. A surfaces(60,62) of two chips are arranged to be faced each other through a film carrier. Bonding pads of two chips are connected electrically to a conductive wire(56) through bumps(64,66). An epoxy is injected to a vacant space between two chips to form an insulation chemical composite.</p>
申请公布号 KR20000052097(A) 申请公布日期 2000.08.16
申请号 KR19990002950 申请日期 1999.01.29
申请人 UNITED MICROELECTRONICS CORP. 发明人 SHUANMIN CHI;LINCHENG TAE
分类号 H01L25/18;H01L23/498;H01L23/522;H01L25/065;H01L25/07;(IPC1-7):H01L23/522 主分类号 H01L25/18
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