发明名称 OUTPUT CIRCUIT AND SYNCHRONOUS DRAM USING THE SAME
摘要 PROBLEM TO BE SOLVED: To secure the effective widthness of output data at a high frequency by making a first level converting circuit converting the power source level of data from a HIGH output side and a second level converting circuit the power source level of data from a LOW output side among data which are outputted by a latch circuit have the same constitution to reduce variation in output time. SOLUTION: When a latch circuit 50 input two output data, an output permitting signal, an output clock signal and an output clock bar signal, it latchingly outputs the inputted data. Level converting circuits 60a, 60b respectively convert power source levels of data of the HIGH output side and of data of the LOW output side among data which are outputted by the circuit 50 to output them to an output transistor part 70. Thus, a time when the piece of HIGH data is outputted and a time when the piece of LOW data outputted can be equalized by making the constitution of the level converting circuit 60b of the LOW output side to be the same as that of the level converting circuit 60a of the HIGH output side.
申请公布号 JP2000228085(A) 申请公布日期 2000.08.15
申请号 JP19990028961 申请日期 1999.02.05
申请人 NEC CORP 发明人 KITAMURA MAMORU
分类号 G11C11/409;G11C11/407;(IPC1-7):G11C11/409 主分类号 G11C11/409
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