| 摘要 |
PROBLEM TO BE SOLVED: To fix the C/N ratio of a frequency synthesizer device with respect to the oscillation frequency of a voltage-controlled oscillator. SOLUTION: A PLL synthesizer is constituted of a first frequency divider 2, a phase comparator 3, a loop filter 4, and a second frequency divider 5. A frequency dividing ratio control circuit 6 controls the frequency-dividing ratio of the first frequency divider 2, so that the ratio changes with time and the time average value of the frequency dividing ration contains a decimal fraction. When the oscillator 1 is made to generate a specific frequency, a signal obtained by delaying the phase of the output signal of the first frequency divider 2 is used as the clock of the control circuit 6. The variation of the C/N ratio of the synthesizer can be eliminated by means of the frequency of the oscillator 1, and the locking-up time of the synthesizer device can be shortened. |
