| 摘要 |
PROBLEM TO BE SOLVED: To change a feedback signal and to perform the phase locking of a secondary phase-locked loop by making a phase detector output a phase error signal representing comparison between an input clock signal and the feedback signal, making a loop filter receive the phase error signal, outputting an error correction signal and generating an output signal for a phase-locked loop. SOLUTION: A phase-locked loop(PLL) circuit 300 includes a 1st multiplexer, that is connected so as to receive a 1st input clock signal 322A from a 1st clock source and to receive a 2nd input clock signal 322B from a 2nd clock source. The multiplexer is controlled by a signal from an OR block connected, so as to receive a selection clock input SEL-CLK and an output of a switching logic 330. The selection clock input sets the identification of a primary clock input. The switching logic 330 receives a control input 332 and outputs a state output 331. |
