| 摘要 |
PCT No. PCT/IT96/00198 Sec. 371 Date May 5, 1999 Sec. 102(e) Date May 5, 1999 PCT Filed Oct. 30, 1996 PCT Pub. No. WO97/49087 PCT Pub. Date Dec. 24, 1997A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A read voltage generating circuit is adapted to an input supply voltage and provides a read voltage to the memory cells. The read voltage generating circuit includes a voltage boosting circuit providing the read voltage greater than the input supply voltage.
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