发明名称 |
Digital clock recovery loop |
摘要 |
A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising: a voltage controlled oscillator having a control node and an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.
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申请公布号 |
US6100765(A) |
申请公布日期 |
2000.08.08 |
申请号 |
US19990397484 |
申请日期 |
1999.09.16 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
PAX, GEORGE E.;O'TOOLE, JAMES E.;GRIFFIN DAN M |
分类号 |
H03L7/089;H03L7/113;H04B1/707;H04L7/033;(IPC1-7):H03L1/00;H03L7/89;H03L7/18 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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