| 摘要 |
A semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors includes, a) providing an electrically insulative device isolation mass between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges; and b) providing a pair of electrically conductive transistor source/drain diffusion regions within the active area regions, one of the conductive source/drain diffusion regions being received within one of the active area regions and being associated with one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other of the active area regions and being associated with another field effect transistor, the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective mass laterally outermost edges to space the transistor source/drain diffusion regions edges away from the isolation mass. Integrated circuitry having adjacent electrically isolated field effect transistors produced according to the method and other methods is also disclosed. The invention also contemplates spacing one electrically conductive (heavy implant) diffusion region of one of adjacent field effect transistors away from the device isolation mass. Regardless, preferred spacing of the implant from the device isolation is at least 0.01 micron.
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