发明名称 VITERBI DECODER
摘要 PURPOSE: A viterbi decoder is provided to speed up the modem by using a CSA and a 5-bit incrementer for adding a present BM value and a past accumulated PM value. CONSTITUTION: A branch metric units(BM) are constituted with 3-bit CSA. A path metric memory units(PMM) stores a hamming distance value accumulated up to the present state for ACS operations for next states. An adder compare select units(ACS) is constituted with a comparator having a CSA and a 5-bit incrementer for adding an output of the units(BM) and a previously accumulated PM value stored in the units(PMM) and uses a metric rescaling mode for the least PM in each node. A trace back units(TBM) decodes path information in a radix-4 mode.
申请公布号 KR20000049852(A) 申请公布日期 2000.08.05
申请号 KR20000023691 申请日期 2000.05.03
申请人 JUNG, JI WON;SEJIN INFORMATION AND COMMUNICATIONS LTD. 发明人 KIM, YONG OK;JUNG, JI WON
分类号 H03M13/41;(IPC1-7):H03M13/41 主分类号 H03M13/41
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