| 摘要 |
PROBLEM TO BE SOLVED: To provide a time out preferential processing timer circuit capable of processing timers in time out in turn and improving the reliability of a set timer value. SOLUTION: In the case where timers simultaneously get time-out in decrement period, the time-out preferential processing circuit 3 stores the timer addresses in turn. While CPU 1 takes a time out buffer lead motion, the time out buffer value can be read by the turn having stored in the time out priority processing circuit 3. By this reason, even if the next timer gets time out before ending time out processing, the time out buffer value is not rewritten and by performing the time out processing in one decrement period after the time out, the timer set error can be within one decrement period.
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