| 摘要 |
PROBLEM TO BE SOLVED: To support plural processors of different types which are connected to plural memory arrays and input/output devices via one or >=2 input/output buses. SOLUTION: At least one processor has a master device and a slave device, and the slave device has one or more memory ports which are connected to an MAU and a memory control unit(MCU) 50 which controls the accesses to the MAU via the memory ports. The MCU 50 has a switch network 54 which is connected to one or more memory ports to transfer the data between the master device and one or more memory ports, a switch arbitration means 58 which performs the arbitration for the network 54 and a port arbitration means PAU which performs the arbitration for one or more memory ports. |
