MEMORY PORT ARBITRATING METHOD

摘要

PROBLEM TO BE SOLVED: To support different kind of processors connected to memory arrays and input/output devices by assigning priority to respective devices. SOLUTION: Each processor is equipped with a memory control unit(MCU) 50, connected to a cache control unit(CCU) 49 equipped with a data cache (D cache) 51 and an instruction cache (I cache) 52, and an input/output port 53. An MPU 50 is equipped with an interface and as switch network 54. The switch network 54 receives instructions and data requests from the CCU 49. A switch arbitration unit 58 assigns priority to the requests and passes the requests to corresponding port interfaces p0 to pN or the interface according to the addresses added to the requests.