发明名称 MULTIPLEX CELL-DISASSEMBLING PROCESSOR AND MULTIPLEX CELL-DISASSEMBLING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a multiplex cell-disassembling processor with which a buffer capacity and quantity of buffer management information can be reduced and a cell-disassembling time can be decreased. SOLUTION: A header/payload separation processing section 11 separates a header part and a payload data part of an ATM cell. A loss error-in delivery processing section 12 conducts cell loss error in delivery detection, cell compensation at detection of cell loss, and cell abort at detection of cell error-in delivery. A common buffer section 14 stores in advance the pattern of a dummy cell and has banks in units of cells storing the payload part of the received ATM cell. A CAM section 16 stores data correlating an ATM/AAL header with an address where the payload is stored. A complementary FIFO section 17 stores data correlating the cell loss number detected by the loss error-in delivery processing section 12, the ATM header and the AAL header with the addresses in which the payload is stored.
申请公布号 JP2000216793(A) 申请公布日期 2000.08.04
申请号 JP19990017878 申请日期 1999.01.27
申请人 NEC CORP 发明人 SOEDA YASUYUKI
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
代理机构 代理人
主权项
地址