发明名称 CACHE MEMORY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To actualize interleaving-system constitution in the cache memory circuit without using the cache memory circuit by fractionizing it into banks. SOLUTION: The inside of a cache memory circuit is divided into areas by groups and column address lines 341 to 344 by the divided groups, column decoders 351 to 354, and column selector circuits 381 to 384 are provided; and an array reference address is supplied by a row decoder 310 to a memory cell array 330 through a row select line 320 and column addresses by the groups are supplied to a column select circuit through the column address line by the column decoder.
申请公布号 JP2000215103(A) 申请公布日期 2000.08.04
申请号 JP19990013077 申请日期 1999.01.21
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 KAWAMOTO KOJI;ITOI TOMONAGA;HIRAOKA TORU;KUROKAWA HIROSHI
分类号 G06F12/08;G11C11/41;(IPC1-7):G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址