| 摘要 |
PCT No. PCT/SE96/00246 Sec. 371 Date Apr. 20, 1998 Sec. 102(e) Date Apr. 20, 1998 PCT Filed Feb. 26, 1996 PCT Pub. No. WO97/19412 PCT Pub. Date May 29, 1997A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-22 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-22 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.
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