| 摘要 |
PCT No. PCT/IT96/00199 Sec. 371 Date Jun. 7, 1999 Sec. 102(e) Date Jun. 7, 1999 PCT Filed Oct. 30, 1996 PCT Pub. No. WO97/49088 PCT Pub. Date Dec. 24, 1997A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.
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