| 摘要 |
PROBLEM TO BE SOLVED: To reduce a chip size, while non-arranged region for preventing no- wiring is dispensed with to prevent increase in chip size by providing a plurality of physical patterns to a single-kind functional cell. SOLUTION: A trunk power source wiring 2 and a trunk ground wiring 3 are provided at the peripheral part of a semiconductor integrated circuit device 1 generated by automatic arrangement/wiring, while an reinforcing power source wiring 4 and reinforcing round wiring 5 at the central part. The reinforcing power source wiring 4 and reinforcing ground wiring 5 are generated at second layer wiring. On a cell array 6, a power source wiring and ground wiring are provided by first layer wiring in the cell array direction, connecting the trunk power source wiring 2, trunk ground wiring 3, reinforcing power source wiring 4, and reinforcing ground wiring 5. A functional cell 7 provided directly below the reinforcing power source wiring 4 and reinforcing ground wiring 5 comprise the physical pattern of a functional cell, which has no 2-layer metal wiring pin. Thus, since the functional cell 7 can be arranged even at a part where arrangement was not possible, chip size can be reduced.
|
