METHOD FOR VERIFYING EQUIVALENCE SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To verify a logically equivalent circuit. SOLUTION: Respective circuits are provided with steps F1 and F3 in which a serial contraction processing where elements connected in series are converted into serial virtual elements and parallel contraction processing where elements connected in parallel are converted into parallel virtual elements are performed and steps F2 and F4 where compound gate contraction processing is performed to a reference side circuit where the serial contraction processing and the parallel contraction processing are performed and a check side circuit is performed. Further, the compound gate contraction processing is provided with a step in which the serial virtual elements and the parallel virtual elements are converted into a circuit consisting of virtual elements which is equivalent to that when a common term is derived by distributive law of logical algebra when the serial virtual elements are considered as the conjunction of the logical algebra and the parallel virtual elements are considered as the disjunction of the logical algebra.