| 摘要 |
<p>A data processing apparatus for effectively and quickly processing a large amount of data by processors, e.g., for detection of motion vectors in image processing. An SDMD circuit (4) controlled by a CPU (2) is connected with a WORKRAM (12) through a local bus (8) that is wider than the data bus (6) of the CPU (2). An address bus (10) is connected commonly with the SDMD circuit (4), the WORKRAM (12), and the CPU (2). The CPU (2) integrally controls the SDMD circuit (4) and the WORKRAM (12) to perform high-speed data processing.</p> |
