| 摘要 |
PURPOSE: A full adder is provided to improve the capabilities of electronic circuits by employing NMOS Pass Transistor Logic in forming a carry and sum section. CONSTITUTION: A full adder includes a latch-style swing restoration section that comprises numerous CMOS inverters. This device comprises a carry section(44) which is composed of CMOS Pass Transistor Logic Network, a latch-style swing restoration section(41,71), a Sum section(74) which comprises a Sum generator section(74) constituted by the CMOS Pass Transistor Logic Network. The device improves the capacity of electronic circuits by increasing the speed of electronic circuits. The circuit requires less room than the prior circuits using PMOS and prevents the Non-full Swing phenomenon.
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