STRUCTURE OF SYNCHRONOUS DRAM

摘要

PURPOSE: A structure of a synchronous DRAM is provided to reduce a size of the entire semiconductor chip by reducing a number of a data bus line sense amplifier/latch circuit unit to a half. CONSTITUTION: A data bus line sense amplifier/latch circuit(120) includes a transmission transistor(124) receiving data from a bank and transmitting the data to a data bus line sense amplifier and a latch circuit. The data bus line sense amplifier and the latch circuit are placed between two banks(100,110) to share each other. By a control signal alerting the column action output from respective bank, a data path of the bank and the data bus line sense amplifier/latch circuit escape from a simultaneous occurrence of column actions of the banks. Even if the capacity of a memory is increased, the number of sense amplifier/latch circuits connected to the banks is reduced in half. Thereby, the entire area of a chip is reduced.