| 摘要 |
In a plurality of shift registers which receive Mxn-tuple speed data divided into plural parts, execute modulation of the data, and output modulated data as n-tuple speed data, a period of time required from a start of inputting Mxn-tuple speed divided data as a modulation object to an end of outputting n-tuple speed modulated data is set within one period of an Mxn-tuple speed frame clock.
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