Processor and instruction set with predict instructions

摘要

A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.