| 摘要 |
An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, fb. An image of the 60x bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY- and SHD-, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be "out-of-phase" with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, fo. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, fo.
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