发明名称 |
Method of fabricating interconnect lines and plate electrodes of a storage capacitor in a semiconductor device |
摘要 |
A method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.
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申请公布号 |
US6090662(A) |
申请公布日期 |
2000.07.18 |
申请号 |
US19960698257 |
申请日期 |
1996.08.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, BYEUNG-CHUL |
分类号 |
H01L21/768;H01L21/28;H01L21/8242;H01L27/108;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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