发明名称 |
SYSTEM & METHOD FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CIRCUIT |
摘要 |
<p>While dispatch circuitry operates in a first power mode, per cycle of the dispatch circuitry, up to N number of instructions are dispatched to execution circuitry for execution, where N is an integer number and N>1. While the dispatch circuitry operates in a second power mode, per cycle of the dispatch circuitry, up to M number of instructions are dispatched to the execution circuitry for execution, where M is an integer number and 0<M<N.</p> |
申请公布号 |
KR100261639(B1) |
申请公布日期 |
2000.07.15 |
申请号 |
KR19970039160 |
申请日期 |
1997.08.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LOPER, ALBERT J.;MALLICK, SOUMMYA |
分类号 |
G06F1/04;G06F1/32;G06F9/30;G06F9/38;G06F9/46;G06F9/48;G06F12/08;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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