发明名称 CIRCUIT FOR CAUSING FPLL TO LOCK IN DESIRED PHASE
摘要 PURPOSE: An FPLL(Frequency and Phase Locked Loop) is provided to easily adjust the signal phase and polarity to be locked to a phase which is determined previously. CONSTITUTION: The FPLL further includes an automatic phase locking unit(50) having a lock indicator(40) and a lock switch(34). A de-modulator(18) de-modulates an input signal into two oscillator signals which have 90 degree phase difference from each other. The lock switch(34) receives one out of an automatic frequency control loop filter(30) and a limiter(26) and two signals. The lock indicator(40) generates a lock indicator signal which represents the locking frequency of the frequency and phase locking circuit. The automatic phase locking unit(50) forces the frequency and phase locking circuit to the phase generating one polarity of the selected signal out of the two polarities of the output signal.
申请公布号 KR100261805(B1) 申请公布日期 2000.07.15
申请号 KR19970037926 申请日期 1997.08.08
申请人 LG ELECTRONICS INC. 发明人 MYCYNET G, VICTOR;OTTO W, LEIF
分类号 H04N5/455;H03L7/087;(IPC1-7):H04N5/455 主分类号 H04N5/455
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