发明名称 CIRCUIT FOR GENERATING NEGATIVE VOLTAGE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A negative voltage generating circuit is provided to economize a current consumption of a body bias applied to a P-well. CONSTITUTION: A negative voltage generating circuit comprises a Vpp detector(21), a switch(22), a controller(23) and a latch circuit(24). The Vpp detector(21) is operated responsive to an inverted version of an output signal(cut) of the controller(23), and detects whether a voltage(Vpp) reaches a predetermined voltage level. The Vpp detector(21) outputs a low level signal(det) when the voltage(Vpp) reaches a predetermined voltage level. The switch(22) transfers an output signal of the Vpp detector(21) to the latch circuit(24) in response to the output signal(cut) of the controller(23). The latch circuit(24) latches the signal transferred through the switch(22) to output the latched signal as a pump start signal(pump_strt) through an inverter(25). The controller(23) consists of an inverter(30) and an NOR gate(31), and generates the signal(cut) in response to the pump start signal(pump_strt) and a pump up signal(pwrup).
申请公布号 KR20000044594(A) 申请公布日期 2000.07.15
申请号 KR19980061093 申请日期 1998.12.30
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 LEE, SEONG HUN
分类号 H03K19/00;(IPC1-7):H03K19/00 主分类号 H03K19/00
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