| 摘要 |
PURPOSE: A circuit for controlling a data output buffer is provided to secure a data access time and a data maintenance time suitable for a kind of load. CONSTITUTION: A circuit for controlling a data output buffer(602) drives terminate load or unterminated load by being constructed with a pull-up element and a pull-down element. And the circuit comprises a delay circuit(606), a load detection circuit(610), and a delay control circuit(608). The delay circuit(606) generates a first output by receiving a first control signal and delaying the received signal for a predetermined time. The load detection circuit(610) is enabled by the first output, detects a load condition by receiving a second output from the output buffer. The load detection circuit(610) generates a second control signal of a logical value, one "1", when the load condition is a terminated load, and generates a second control signal of a logical value, zero "0", when the load condition is an unterminated load. And the delay control circuit(608) is controlled by the second control signal, controls to secure a data output maintenance time of the data output buffer when the logical value of the second control signal is one "1", and control to secure a data access time of the data output buffer when the logical value of the second control signal is zero "0".
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