OVERLAY MEASUREMENT PATTERN OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: An overlay measurement pattern of a semiconductor device is provided to improve overlay accuracy by preventing a side distortion of a parent vernier and a vernier. CONSTITUTION: An overlay measurement pattern of a semiconductor device comprises a semiconductor substrate(100), a parent vernier(110), and a vernier(120). The semiconductor substrate comprises a scribe line for partitioning dies. The parent vernier is formed with an inner pattern and an outer pattern of a rectangle pattern according to predetermined intervals. The inner pattern and the outer pattern is formed on the scribe line. The vernier is formed with the rectangle pattern formed at an inner portion of the inner pattern of the parent vernier.