发明名称 ARITHMETIC PROCESSOR AND INSTRUCTION ORDER CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To further improve frequency by judging whether or not a fetched instruction or an instruction stored in an instruction storage means can be executed according to information regarding the use states of registers. SOLUTION: For example, when two pipeline units 6-1 and 6-2 are provided, this dynamic VLIW system is provided with independent Pending Queues 2-1 and 2-2 for slots 1 and 2, respectively, so as to save an instruction fetched from a normal instruction sequence as an execution waiting instruction if it can not be executed immediately. Further, out-of-order is realized by using a table called a score board 4 for managing information regarding the use states of the registers for each register. an atom which is not executed among atoms of a fetched VLIW instruction is saved in the Pending Queues 2-1 and 2-2 until its execution becomes possible.
申请公布号 JP2000194555(A) 申请公布日期 2000.07.14
申请号 JP19980373380 申请日期 1998.12.28
申请人 TOSHIBA CORP 发明人 ASANO SHIGEHIRO;YOSHIKAWA YOSHIFUMI
分类号 G06F9/38;G06F9/30;(IPC1-7):G06F9/38 主分类号 G06F9/38
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