| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern-forming apparatus for logic circuits which has a means for enhancing a formation success rate for a test pattern enabling a plurality of target failures to be detected. SOLUTION: The apparatus has a C0 value/C1 value-calculating part 115 for calculating a difficulty degree in setting a signal value 0 and a difficulty degree in setting a signal value 1 in generating a test without restrictions with influences of an existing signal line taken into account, an OB value-calculating part 120 for calculating a difficulty degree in propagating the signal value to a circuit output in the test generation without restrictions, a C0' value/C1' value-calculating part 155 for calculating a difficulty degree in setting the signal value 0 and a difficulty degree in setting the signal value 1 in generating a test with restrictions, an OB' value-calculating part 160 for calculating a difficulty degree in propagating the output value to the circuit output in the test generation with restrictions with influences of the existing signal line taken into account, and a target failure-selecting part 170 for selecting a target failure in the test generation with restrictions with use of a difficulty degree in the test generation with restrictions which is a synthesis of the difficulty degree in setting the signal value 0, difficulty degree in setting the signal value 1 and difficulty degree in propagating the signal value to the circuit output in the test generation with restrictions.
|
