| 摘要 |
A waveform generating device in which the timing accuracy is improved and the scale of the hardware is simplified. Delay data for generating a set pulse is selected from delay data according to test logical data PAT and waveform mode information. The selected delay data, delay data for skew adjustment, and fraction data in test cycles are calculated. Integer delay data Sa and fraction delay data Sb are produced from the output of the calculation and fed to a counter delay circuit (50). An effective flag for generating a set pulse the test cycle timing of which is delayed by the delay time corresponding to the integer delay data and the associated fraction delay data are outputted from the counter delay circuit. The effective flag is delayed according to the associated fraction delay data to generate a set pulse. Similarly a reset pulse is generated to set/reset an S-R flip-flop (26), thereby outputting a desired waveform.
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