发明名称 |
CIRCUIT ARRANGEMENT AND METHOD WITH STATE-BASED TRANSACTION SCHEDULING |
摘要 |
A data processing system (10), circuit arrangement, and method rely on state information to prioritize certain transactions relative to other transactions when scheduling transactions in a data processing system (10). In one implementation, as a result of the recognition that in many shared memory systems cached data having a modified state is accessed more frequently than cached data having a non-modified state, transactions associated with modified cached data are prioritized (100, 120) relative to transactions associated with non-modified cached data, thereby reducing the latency of such modified transactions. Any concurrent increase in latency for non-modified transactions is more than offset by the decreased latency of modified transactions, resulting in an overall reduction in system latency.
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申请公布号 |
WO0041076(A2) |
申请公布日期 |
2000.07.13 |
申请号 |
WO1999US29886 |
申请日期 |
1999.12.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MOUNES-TOUSSI, FARNAZ;FREERKSEN, DONALD, LEE |
分类号 |
G06F12/08;G06F13/18;(IPC1-7):G06F9/46 |
主分类号 |
G06F12/08 |
代理机构 |
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地址 |
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