发明名称 |
LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device |
摘要 |
<p>An LVDS interface for a programmable logic device uses phase-locked loop ("PLL") circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.</p> |
申请公布号 |
EP1018805(A2) |
申请公布日期 |
2000.07.12 |
申请号 |
EP19990310576 |
申请日期 |
1999.12.24 |
申请人 |
ALTERA CORPORATION |
发明人 |
SUNG, CHIAKANG;WANG, BONNIE I.;CLIFF, RICHARD G. |
分类号 |
G06F1/08;G06F13/42;G06F1/12;H03L7/07;H03L7/08;H03L7/089;H03L7/18;H04L25/02;H04L25/40;(IPC1-7):H03K5/15;G06F1/10;H03K5/135 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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