| 摘要 |
A digital-to-analog converter system (150) based on a symmetrical circuit (152) comprising matched capacitors (104, 106) for pseudo-passive, serial D/A conversion of a digital input signal x(n). Each bit x(n,k) of x(n) is converted by selecting one of the two in each capacitor pair (104, 106) as the driving one, and charging it to plus/minus the reference voltage according to the value of x(n,k). The other capacitor in each capacitor pair (104, 106) stores the previously generated voltage signal representing the bits of x(n) less significant than the bit x(n,k) being processed in the considered cycle k of the serial conversion process. After the driving capacitor has been charged according to x(n,k), the capacitors in each capacitor pair (104, 106) are connected in parallel. Voltage signals representing the bits of x(n) having significance of up to and including x(n,k) is thereby generated on the capacitors (104, 106). Because the circuit (152) is symmetrical, a selector signal t(n,k) may designate arbitrarily which capacitor in each capacitor pair (104, 106) be the driving one, and which be the storing one. The selector signal t(n,k) may attain a new value for the processing of each bit x(n,k). The selector signal t(n,k) is generated such that the error signal induced by mismatch of the matched capacitor pairs (104, 106) will be noise-like and have a reduced power spectral density in the selected signal band. The selector signal t(n,k) is particularly simple to generate if each sample of the input signal x(n) is repeated twice, which it will be when using a popular type of interpolation filters. When each serial conversion cycle is completed, the generated voltage will represent x(n); only then, the capacitor pairs (104, 106) are connected to the driving opamps (118A, 118B).
|
