| 摘要 |
<p>A phase-locked loop comprising: a controllable oscillator (1) for supplying an output signal (So) having a frequency which is dependent on a control signal (Sc), feedback means (2) for supplying a feedback signal (Sh) having a frequency which is proportional to the frequency of the output signal (So), first error signal-generating means (3) for generating a first error signal (Se) which is a measure of an average difference in phase between the feedback signal (Se) and a reference signal (Sref), second error signal-generating means (4) for receiving the first error signal (Se) and generating a second error signal (Sa), comprising A/D conversion means (4a) for converting the first error signal (Se) into a digital signal (Sd), digital memory means (4b) for memorizing the digital signal (Sd), and D/A conversion means (4c) for converting the digital signal (Sd) into the second error signal (Sa). The phase-locked loop has a first operational state in which the digital signal (Sd) memorized in the digital memory means is dependent on the reference signal (Sref), and a second operational state in which the digital signal (Sd) is independent of the reference signal (Sref). In addition, the phase-locked loop comprises switching means (9) for selecting the control signal (Sc) from the first error signal (Se) and the second error signal (Sa). In the first operational state, the first error signal (Se) is the control signal (Sc), and in the second operational state, the second error signal (Sa) is the control signal (Sc).</p> |
