发明名称 ARRANGEMENT FOR INNER CIRCUITS OF SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE: A semiconductor memory device is provided to reduce size and power dissipation. CONSTITUTION: Plural input buffers/shift blocks(211) are arranged adjacently while adjacently arranging plural output buffers/shift blocks(212). Thus, one clock line(261,262) is required for transferring each input/output control clock signal(sclk,tclk). Load on a delay synchronous loop circuit(241) driving the input/output control clock signals is decreased. Thus, the size of output drivers of the delay synchronous loop circuit is reduced. Accordingly, power dissipation and size of the delay synchronous loop circuit are decreased. In addition, the power dissipation and size of a Rambus DRAM(dynamic random access memory) semiconductor device(201) is decreased.
申请公布号 KR20000040174(A) 申请公布日期 2000.07.05
申请号 KR19980055735 申请日期 1998.12.17
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 MUN, BYUNG MO
分类号 G11C11/401;G11C7/00;G11C11/4093;(IPC1-7):G11C7/00 主分类号 G11C11/401
代理机构 代理人
主权项
地址