| 摘要 |
PURPOSE: A wafer level chip scale package(WL-CSP) is provided to prevent a micro-distortion of the package. CONSTITUTION: A package(200) includes a semiconductor chip(110) having bonding pads(112) formed on an active surface(114). The bonding pads(112) are electrically connected with metal wirings(120) and then redistributed to ball pads(122). The package(200) further includes a dielectric layer(130) covering the active surface(114) and the metal wirings(120), and solder balls(140) formed on the ball pads(122) exposed through the dielectric layer(130). In addition, the package(200) includes dummy pads(124) formed on the active surface(114), not electrically connected with the bonding pads(112), and exposed through the dielectric layer(130). Moreover, dummy solder balls(150) are formed on the dummy pads(124) at similar intervals to the solder balls(140). Therefore, the package(200) has a regular distribution of solder balls(140,150), and thereby the package(200) can be stably jointed on a main board.
|
