发明名称 |
State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet |
摘要 |
A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request. When the device of the present invention is in multiple-register access mode, a read or write operation addressed to a selected register is interpreted as a request to read or write from all registers in a defined group of registers and the state machine directs the operation of the device to accomplish a read from or write to all of the registers in the group. When the device is in single-register mode, operations addressed to the selected register cause normal read or write operation to be executed with respect to that register.
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申请公布号 |
US6085258(A) |
申请公布日期 |
2000.07.04 |
申请号 |
US19980100270 |
申请日期 |
1998.06.19 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
DREYER, STEPHEN F.;HU, RONG-HUI |
分类号 |
G06F13/12;H04L29/10;(IPC1-7):G06F13/00;G06F9/00;G06F15/00 |
主分类号 |
G06F13/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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