| 摘要 |
PROBLEM TO BE SOLVED: To provide a lock discrimination circuit for PLL that raises a level of a lock discrimination gate just after a lock state is discriminated so as to reduce a period for a through-current to flow thereby reducing the power consumption. SOLUTION: Just after the lock discrimination circuit discriminates a lock state, an input level of the lock discrimination circuit that has been an intermediate level is forcibly pulled up so as to reduce a through-current of a lock discrimination gate. The input level of the lock discrimination circuit is pulled up by using a delay circuit 8 whose operation is started by lock discrimination to turn on a pull-up transistor(TR) Tr. B only for a prescribed time. |
