发明名称 BUS ARBITRATION CONTROLLER AND BUS ARBITRATION CONTROL SYSTEM USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a bus arbitration controller capable of operating an appropriate bus arbitration in accordance with the change of the level of the load of a device. SOLUTION: A select signal generator 20 generates a select signal based on the counter values of device #0-3 bus access counter circuits 16-19. Devices number selectors 21-24 output device numbers instructed by the select signal to priority registers 25-28. The priority registers 25-28 store the device numbers from the device number selectors 21-24 when one of comparators 12 and 14 indicates coincidence. A priority pointer 29 stores the start point of a priority ring to be used by a bus arbitrating circuit 30. The bus arbitrating circuit 30 decides the priority of buses based on the contents of the priority registers 25-28 and the priority pointer 29, and outputs a bus use permission signal to each device 3-6.
申请公布号 JP2000187640(A) 申请公布日期 2000.07.04
申请号 JP19980364026 申请日期 1998.12.22
申请人 NEC ENG LTD 发明人 SUZUKI KUNIHIKO
分类号 G06F13/362;(IPC1-7):G06F13/362 主分类号 G06F13/362
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