| 摘要 |
A ternary content addressable memory (CAM) (800) having a massive, parallel shift capability is disclosed. The CAM (800) includes an array of CAM cells (802(1,1) to 802(1,4)), each of which includes a data value register (804(1,1) to 804(1,4)) and a mask value register (806(1,1) to 806(1,4)). To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a higher row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes an upper data input (UD) coupled the output of a CAM cell in the higher row. To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a lower row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes a lower data input (LD) coupled the output of a CAM cell in the lower row.
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